A 158 Ms/s Jpeg 2000 Codec with a Bit-plane and Pass Parallel Embedded Block Coder

This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on a bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a codeblock. An upper BPC transfers significance states and sign bits to a lower BPC via a first-in-first-out buffer (FIFO) to synchronize BPCs themselves. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1column gap. The bit-modeling passes in the bitplane also overlap in time with the same gap. These methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 μm process. The core area is 4.7 × 4.7 mm and the frequency is 160 MHz. It is applicable to a wireless PC display.